From owner-acpi-jp@jp.freebsd.org  Wed Dec 15 23:47:36 1999
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Date: Wed, 15 Dec 1999 23:47:27 +0900
From: Mitsuru IWASAKI <iwasaki@jp.freebsd.org>
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X-Sequence: acpi-jp 165
Subject: [acpi-jp 165] Help!! PTS for PORTEGE 3110CT
Errors-To: owner-acpi-jp@jp.freebsd.org
Sender: owner-acpi-jp@jp.freebsd.org
X-Originator: iwasaki@jp.freebsd.org

PORTEGE 3110CT $BMQ$N(B PTS $B$r=q$$$F$$$^$9$,:$$C$F$$$k$N$G(B
$B=u$1$F$/$@$5$$!#(B
# $B$$$A$*$&!"%$%s%?%W%j%?$K$b4X78$"$kOC$@$H;W$$$^$9!#(B

$BEE8;%\%?%s%$%Y%s%H$r=&$C$F(B PTS $B$r<B9T$7$F$$$k$s$G$9$,!"(B
sleeping state $B$,$A$c$s$HA+0\$;$:!"(Bsoft off $B$H$+$8$c$J$/$F(B
reboot $B$7$F$/$l$^$9!#(B

PTS $B$G$O(B SystemMemory $B$N(B OperationRegion $B$K$"$k(B Field $B$r(B
$B$$$8$k$H$3$m$,$"$j!"$5$i$K$3$l$O(B ACPI $B4X78$N(B SMAP $B30$K$"$k(B
$BNN0h$i$7$$$N$G!"$d$`$r$($:(B pmap_enter() $B4X78$r%J%^$G;H$C$F(B
$BJ*M}%a%b%j$NFbMF$r=q$-49$($F$$$^$9(B ($B$3$N$"$?$j$,$"$d$7$$$+$b(B)$B!#(B

$B6l$7J6$l$K(B printf() $B$H$+$7$F$_$?$s$G$9$,!"$A$g$C$H5M$^$C$A$c$C$?(B
$B$_$?$$$J$N$G!"$I$J$?$+=q$-$+$1$N%3!<%I$H(B dmesg $B=PNO$r8+$F%"%I%P%$%9(B
$B$$$?$@$1$^$;$s$G$7$g$&$+(B?

--- acpi.c~	Wed Dec 15 02:27:35 1999
+++ acpi.c	Wed Dec 15 23:05:46 1999
@@ -1104,10 +1105,20 @@
 
 #define If(x)	if(x)
 
+#define Else	else
+
 #define LNot(x)	!(x)
 
+#define LOr(op1, op2)		(op1) || (op2)
+
+#define LAnd(op1, op2)		(op1) && (op2)
+
 #define LEqual(op1, op2)	op1 == op2
 
+#define LLess(op1, op2)		op1 < op2
+
+#define LGreater(op1, op2)	op1 > op2
+
 #define Store(VAL, OBJ)	\
 	/* XXX Supports StstemIO RegionSpace only */ \
 	acpi_registers_input(OBJ, &tmp, OBJ##_LEN); \
@@ -1117,6 +1128,9 @@
 #define Or(op1, op2, op3) \
 	op3 = op1 | op2;
 
+#define And(op1, op2, op3) \
+	op3 = op1 & op2;
+
 #define One	0x1
 
 #define Zero	0x0
@@ -1557,6 +1571,272 @@
 	/* How to implement? */
 }
 
+/*
+ * _PTS and _WAK for PORTEGE 3110CT
+ */
+/*static void*/
+void
+acpi_execute_pts_3110CT(acpi_softc_t *sc, u_int8_t Arg0)
+{
+	/* Original ASL code
+	 *
+        OperationRegion(TRAP, SystemMemory, 0x100b6800, 0x10)
+        Field(TRAP, AnyAcc, NoLock, Preserve) {
+            PAR1,	16,
+            PAR2,	16,
+            PAR3,	16,
+            PAR4,	16,
+            PAR5,	16,
+            PAR6,	16
+        }
+        OperationRegion(SRAM, SystemMemory, 0x100b0000, 0x10000)
+        Field(SRAM, AnyAcc, NoLock, Preserve) {
+            Offset(0x34000),
+            IEAX,	32,
+            IEBX,	32,
+            IECX,	32,
+            IEDX,	32,
+            IESI,	32,
+            IEDI,	32,
+            IEBP,	32,
+            Offset(0x36018),
+            WED0,	1,
+            WED1,	1,
+            WED2,	1,
+            WED3,	1,
+            WED4,	1,
+            Offset(0x36870),
+            BDID,	32,
+            DSPW,	1,
+            VGAF,	1,
+            VWE0,	1,
+            VWE1,	1,
+            PPSC,	1,
+            SPSC,	1,
+            EWLD,	1,
+            EPWS,	1,
+            LCDS,	4,
+            CRTS,	4,
+	}
+	OperationRegion(SRG1, SystemIO, 0xb2, 0x1)
+	Field(SRG1, ByteAcc, NoLock, Preserve) {
+	    TRP4,	8
+	}
+	Method(_PTS, 1) {
+	    If(LOr(\_SB.MEM.VWE0, \_SB.MEM.VWE1)) {
+		Store(0x1, \_SB.MEM.WED2)
+	    }
+	    Else {
+		Store(0x0, \_SB.MEM.WED2)
+	    }
+	    If(LAnd(LNot(LLess(Arg0, 0x1)), LNot(LGreater(Arg0, 0x4)))) {
+		Store(\_SB.MEM.EWLD, \_SB.MEM.PAR1)
+		Store(0x60, \_SB.PCI0.FNC0.SYSR.TRP4)
+	    }
+	    And(Arg0, 0x7, Local0)
+	    Or(Local0, 0x2100, Local0)
+	    SMBR(0xfa00, Local0, 0x0, 0x0, 0xb2)
+	}
+	Method(SMBR, 5) {
+	    Store(Arg0, \_SB.MEM.IEAX)
+	    Store(Arg1, \_SB.MEM.IEBX)
+	    Store(Arg2, \_SB.MEM.IECX)
+	    Store(Arg3, \_SB.MEM.IEDX)
+	    Store(Arg4, \_SB.PCI0.FNC0.SYSR.TRP4)
+	}
+	*
+	*/
+
+	u_int32_t	tmp;
+	u_int32_t	Local0;
+	u_long		ef;
+
+	vm_offset_t	WED;
+	vm_offset_t	BDID;
+	u_int8_t	*WED0;
+	u_int8_t	*DSPW;
+	u_int8_t	VWE0, VWE1, EWLD;
+
+	u_int16_t	*PAR1;
+	u_int32_t	*IEAX, *IEBX, *IECX, *IEDX;
+
+#ifdef ACPI_BUILTIN_STATEPACKAGE
+	struct acpi_system_state_package system_state_package = {{
+		{0x5, 0x0},
+		{0x7, 0x0},
+		{ACPI_UNSUPPORTSLPTYP, ACPI_UNSUPPORTSLPTYP},
+		{0x7, 0x0},
+		{0x0, 0x0},
+		{0x7, 0x0},
+	}};
+#endif
+
+	OperationRegion(SRG1, SystemIO, 0xb2, 0x1)
+	Field(SRG1, ByteAcc, NoLock, Preserve, 0, TRP4,	8)
+
+	sc->system_state_package = system_state_package;
+	sc->system_state_initialized = 1;
+
+	ef = read_eflags();
+	disable_intr();
+	pmap_enter(kernel_pmap, (vm_offset_t)ptvmmap, 0x100b6800, VM_PROT_WRITE, TRUE);
+	WED  = (vm_offset_t)&ptvmmap[((0x36018-0x34000) / 8) & PAGE_MASK];
+	WED0 = WED;
+	BDID = (vm_offset_t)&ptvmmap[((0x36870-0x34000) / 8) & PAGE_MASK];
+	DSPW = BDID + 4;
+	VWE0 = ((*DSPW) >> 2) & 0x01;
+	VWE1 = ((*DSPW) >> 3) & 0x01;
+
+	PAR1 = (u_int16_t *)&ptvmmap[16*0 / 8];
+	IEAX = (u_int32_t *)&ptvmmap[32*0 / 8];
+	IEBX = (u_int32_t *)&ptvmmap[32*1 / 8];
+	IECX = (u_int32_t *)&ptvmmap[32*2 / 8];
+	IEDX = (u_int32_t *)&ptvmmap[32*3 / 8];
+
+printf("BDID = %x, DSPW = %x, *DSPW = %x\n", BDID, DSPW, *DSPW);
+printf("If(LOr(VWE0, VWE1))\n");
+printf(" VWE0 = %x, VWE1 = %x\n", VWE0, VWE1);
+printf(" WED0 = %x\n", WED0);
+printf(" *WED0 = %x -> ", *WED0);
+
+	If(LOr(VWE0, VWE1)) {
+	    /* Store(0x1, \_SB.MEM.WED2) */
+	    *WED0 = (*WED0 & ~(0x1 << 2)) | (0x1 << 2);
+	}
+	Else {
+	    /* Store(0x0, \_SB.MEM.WED2) */
+	    *WED0 = (*WED0 & ~(0x1 << 2)) | (0x0 << 2);
+	}
+printf(" %x\n", *WED0);
+
+	If(LAnd(LNot(LLess(Arg0, 0x1)), LNot(LGreater(Arg0, 0x4)))) {
+printf("If(LAnd(LNot(LLess(Arg0, 0x1)), LNot(LGreater(Arg0, 0x4))))\n");
+	    EWLD = ((*DSPW) >> 6) & 0x01;
+printf(" PAR1 = %x, EWLD = %x\n", PAR1, EWLD);
+
+	    /* Store(\_SB.MEM.EWLD, \_SB.MEM.PAR1) */
+
+printf(" *PAR1 = %x -> ", *PAR1);
+	    *PAR1 = EWLD;
+printf(" %x\n", *PAR1);
+	    /* Store(0x60, \_SB.PCI0.FNC0.SYSR.TRP4) */
+	    Store(0x60, TRP4)
+	}
+	And(Arg0, 0x7, Local0)
+	Or(Local0, 0x2100, Local0)
+
+	/* Method(SMBR, 5) */
+#if 0
+	Store(0xfa00, \_SB.MEM.IEAX)
+	Store(Local0, \_SB.MEM.IEBX)
+	Store(0x0, \_SB.MEM.IECX)
+	Store(ox0, \_SB.MEM.IEDX)
+	Store(0xb2, \_SB.PCI0.FNC0.SYSR.TRP4)
+#endif
+printf(" IEAX = %x, IEBX = %x\n", IEAX, IEBX);
+	*IEAX = 0xfa00;
+printf(" *IEBX = %x -> ", *IEBX);
+	*IEBX = Local0;
+printf("%x\n", *IEBX);
+	*IECX = 0x0;
+	*IEDX = 0x0;
+	Store(0xb2, TRP4)
+
+	pmap_remove(kernel_pmap, (vm_offset_t)ptvmmap,
+		    (vm_offset_t)&ptvmmap[PAGE_SIZE]);
+
+	write_eflags(ef);
+}
+
+static void
+acpi_execute_wak_3110CT(acpi_softc_t *sc, u_int8_t Arg0)
+{
+	/* Original ASL code
+	 *
+        OperationRegion(SRM, SystemMemory, 0x100b6800, 0x10)
+        Field(SRM, AnyAcc, NoLock, Preserve) {
+            Offset(0x10),
+            RDID,	32,
+            RDSN,	32,
+            CAPB,	16
+        }
+	Method(_WAK, 1) {
+	    And(Arg0, 0x7, Local0)
+	    Or(Local0, 0x2180, Local0)
+	    SMBR(0xfa00, Local0, 0x0, 0x0, 0xb2)
+	    Notify(\_SB.PCI0.FNC0.FDD, 0x0)
+	    Notify(\_SB.PCI0.FNC1.IDE0, 0x0)
+	    Notify(\_SB.BAT1, 0x80)
+	    Notify(\_SB.ADP1, 0x80)
+	    Store(0x0, \_SB.MEM.RDID)
+	    Store(0x0, \_SB.MEM.RDSN)
+	    Store(0x5, \_SB.PCI0.FNC0.SYSR.TRP4)
+	    If(LEqual(\_SB.MEM.PAR1, 0x0)) {
+		If(LEqual(0x1151f351, \_SB.MEM.RDID)) {
+		    If(LOr(LNot(LEqual(\_SB.MEM.RDID, \_SB.MEM.DLID)), LNot(LEqual(\_SB.MEM.RDSN, \_SB.MEM.DSRN)))) {
+			Notify(\_SB.PCI0.DOCK, 0x0)
+		    }
+		}
+	    }
+	    Else {
+		If(\_SB.MEM.DLID) {
+		    Notify(\_SB.PCI0.DOCK, 0x1)
+		}
+	    }
+	    Notify(\_TZ.THRM, 0x80)
+	    If(LEqual(\_SB.MEM.VGAF, 0x1)) {
+		Store(0x1, \_SB.MEM.IESI)
+		Store(0x0, \_SB.MEM.IEDI)
+		SMBR(0xff00, 0x23, 0x20, 0x0, 0xb2)
+		WPSX(0x20, 0x1, 0x0, 0x0)
+		Store(0x0, \_SB.MEM.VGAF)
+	    }
+	    If(LEqual(\_SB.MEM.DOS2, 0x0)) {
+		If(LOr(LNot(LEqual(\_SB.MEM.CTLA, \_SB.MEM.NXLA)), LNot(LEqual(\_SB.MEM.CTCA, \_SB.MEM.NXCA)))) {
+		    Notify(\_SB.PCI0.VGA, 0x80)
+		}
+	    }
+	    DIS(0x14)
+	    SMBR(0xff00, 0x1e, 0x1, 0x0, 0xb2)
+	    Store(0x1, \_SB.MEM.PAR1)
+	    Store(0x60, \_SB.PCI0.FNC0.SYSR.TRP4)
+	    Name(BUFF, Package() {
+		0x0
+		0x1
+	    })
+	    If(LEqual(\_SB.MEM.ACST, 0x0)) {
+		And(\_SB.MEM.BST1, 0x4, Local0)
+		If(LEqual(Local0, 0x4)) {
+		    Store(0x1, Index(BUFF, 0x0, Zero))
+		}
+	    }
+	    Return(BUFF)
+	}
+	Method(WPSX, 4) {
+	    Store(Arg1, \_SB.MEM.IESI)
+	    Store(Arg2, \_SB.MEM.IEDI)
+	    SMBR(0xfe00, 0x23, Arg0, 0x0, 0xb2)
+	    While(LNot(LEqual(\_SB.MEM.OECX, 0x0))) {
+		Store(Arg1, \_SB.MEM.IESI)
+		Store(Arg2, \_SB.MEM.IEDI)
+		SMBR(0xfe00, 0x23, Arg0, 0x0, 0xb2)
+	    }
+	}
+	Method(DIS, 1) {
+	    Store(Arg0, \_SB.MEM.PAR1)
+	    Store(0x0, \_SB.MEM.PAR2)
+	    Store(0x0, \_SB.MEM.PAR3)
+	    Store(0x0, \_SB.MEM.PAR4)
+	    Store(0x0, \_SB.MEM.PAR5)
+	    Store(0x0, \_SB.MEM.PAR6)
+	    Store(0x3, \_SB.PCI0.FNC0.SYSR.TRP4)
+	}
+	*
+	*/
+
+	/* How to implement? */
+}
+
 typedef struct {
 	char		*oemid;
 	char		*oemtblid;
@@ -1589,6 +1869,10 @@
 	{
 		" SONY", "Z0", {0x1310859, 0x1310859},
 		acpi_execute_pts_Z505FX, acpi_execute_wak_Z505FX
+	},
+	{
+		"TOSHIB", "3110CT", {0x19990528, 0x19990528},
+		acpi_execute_pts_3110CT, acpi_execute_wak_3110CT
 	},
 	{ NULL,	NULL, {NULL, NULL}, NULL, NULL}
 };

CPU: Pentium II/Celeron (299.94-MHz 686-class CPU)
  Origin = "GenuineIntel"  Id = 0x66a  Stepping = 10
  Features=0x183f9ff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,MMX,FXSR>
real memory  = 66977792 (65408K bytes)
avail memory = 61259776 (59824K bytes)
Preloaded elf kernel "kernel" at 0xc038d000.
Pentium Pro MTRR support enabled
md0: Malloc disk
npx0: <math processor> on motherboard
npx0: INT 16 interface
ACPI: Found ACPI BIOS data at 0xc00f0170 (<TOSHIB>, RSDT@3fe0000)
acpi0: <TOSHIB> on motherboard
acpi0: ADDR RANGE 3fe0000 10000 (mapped 0xc5816000)
acpi0: ADDR RANGE 100b6e00 200 (mapped 0xc5826e00)
acpi0: RSDT have 1 entries
acpi0: RSDT entry0 FACP
acpi0: 	FACP found
acpi0: 	DSDT found Size=17865 bytes
acpi0: 	FACS Found Size=64 bytes
acpi0: acpi_enable_disable(1) = (81)
acpi0: at 0xb2 irq 9
acpi0: acpi_io_pm1_enable(0) = (100, 0)
acpi0: acpi_io_pm1_enable(1) = (100, 100)
acpi0: acpi_io_pm1_status(0) = (1, 0)
acpi0: acpi_io_pm1_enable(0) = (100, 0)
acpi0: acpi_io_gpe0_status(0) = (0)
acpi0: acpi_io_gpe0_enable(0) = (0)
acpi0: acpi_io_gpe1_status(0) = (0)
acpi0: acpi_io_gpe1_enable(0) = (4000)
acpi0: acpi_io_pm1_control(0) = (1401, 0)
acpi0: acpi_io_pm2_control(0) = (0)
acpi0: acpi_io_pm_timer(0) = (1c50d1)
pcib0: <Host to PCI bridge> on motherboard
[snip]
acpi0: pm1_status intr CALLED
acpi0: acpi_io_pm1_enable(1) = (0, 0)
acpi0: acpi_io_pm1_status(1) = (100, 0)
acpi0: acpi_io_pm1_enable(1) = (100, 0)
BDID = c040250e, DSPW = c0402512, *DSPW = 0
If(LOr(VWE0, VWE1))
 VWE0 = 0, VWE1 = 0
 WED0 = c0402403
 *WED0 = 0 ->  0
 IEAX = c0402000, IEBX = c0402004
 *IEBX = 2010000 -> 2105

syncing disks...
done
Uptime: 50s
Rebooting...

