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To: man-jp-reviewer@jp.freebsd.org
In-Reply-To: Your message of "Sun, 18 Jul 1999 20:40:08 +0900"
	<19990718204008C.kawahara@pine.kuee.kyoto-u.ac.jp>
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Date: Thu, 29 Jul 1999 00:33:43 +0900
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Subject: [man-jp-reviewer 1448] Re: rl.4
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$BKY@n$G$9!#F1$8$/CY$/$J$j$^$7$?!#(B

$B2O86$5$s!'(B
> .It "rl%d: watchdog timeout"
> $B%G%P%$%9$,%M%C%H%o!<%/$K1~Ez$7$J$/$J$C$?$+!"%M%C%H%o!<%/$N(B
> $B@\B3(B($B%1!<%V%k(B)$B$KLdBj$,$"$j$^$9!#(B
  $B@\B3(B ($B%1!<%V%k(B) $B$KLdBj$,$"$j$^$9!#(B

> .It "rl%d: chip is in D3 power state -- setting to D0"
> $B%Q%o!<%^%M!<%8%a%s%H$r%5%]!<%H$9$k%"%@%W%?$K$N$_!"$3$N%a%C%;!<%8$,=P$^(B
> $B$9!#%7%c%C%H%@%&%s;~$K%3%s%H%m!<%i$r%m!<%Q%o!<%b!<%I$K$9$k%*%Z%l!<%F%#%s%0(B
> $B%7%9%F%`$,$"$j!"(BPCI BIOS $B$,%A%C%W$r@_Dj$9$kA0$K$3$N>uBV$K$J$C$F$7$^$$(B
                  $B%A%C%W@_DjA0$K$3$N>uBV$r2r=|$7$J$$(B PCI BIOS $B$,$"$j$^$9!#(B
 $B86J8(B ... and some PCI BIOSes fail to bring the chip out of this state
before configureing it.
 bring the chip out of this state $B$G!"!V%A%C%W$r$3$N>uBV0J30$K$9$k!W$H(B
$B$$$&0UL#$G$O$J$$$G$7$g$&$+!#(B

> $B$^$9!#(BD3 $B>uBV$K$*$$$F!"%3%s%H%m!<%i$O(B PCI $B$N@_Dj$9$Y$F$r<:$&$N$G!"(BBIOS 
> $B$,$=$N$H$-$K%U%k%Q%o!<%b!<%I$K@_Dj$7$J$*$5$J$1$l$P!"@5$7$/@_Dj$9$k$3$H(B
> $B$O$G$-$^$;$s!#%I%i%$%P$O$3$N>uBV$r8!=P$7!"%"%@%W%?$r(B D0 ($B%U%k%Q%o!<(B) 
> $B>uBV$K@_Dj$7$J$*$=$&$H$7$^$9$,!"%I%i%$%P$r40A4$KA`:n$G$-$k>uBV$K$9$k$N(B
> $B$K$O;j$i$J$$$+$b$7$l$^$;$s!#%V!<%H;~$K$3$N%a%C%;!<%8$,8=$l!"%I%i%$%P$,(B
> $B%M%C%H%o!<%/%$%s%?%U%'!<%9$H$7$F%G%P%$%9$r%"%?%C%A$9$k$3$H$K<:GT$9$k$N(B
> $B$J$i!"%G%P%$%9$rE,@Z$K@_Dj$9$k$?$a$K(B 2 $BEYL\$N%o!<%`%V!<%H$r9T$&I,MW$,(B
> $B$"$j$^$9!#(B

> .Fx
> $B$N%V!<%HA0$K%7%9%F%`$NEE8;$r@Z$l$P!"%+!<%I@5>o$K@_Dj$5$l$^$9!#(B
                                           $B$,(B

> $B%U%l!<%`$,<u?.$5$l$?$3$H$rCN$i$;$k3d$j9~$_$,5/$-(B
> $B$?$H$-$K!"%I%i%$%P$,$3$N%U%l!<%`$r=hM}$7$F$$$k4V$K<!$N%U%l!<%`$r<u?.%P%C(B
> $B%U%!$K%3%T!<$9$k=hM}$r9T$&$3$H$,$G$-$^$9!#%A%C%W$,<!$N%U%l!<%`$N;D$j$r(B 
                            $B2DG=@-$,$"$j$^$9!#(B
> DMA $B$7$F$7$^$&A0$K!"%I%i%$%P$,:G=i$N%U%l!<%`$r=hM}$7=*$($?$J$i!"%A%C%W(B
> $B$,<!$N%U%l!<%`$N$9$Y$F$r(B DMA $B$9$k$h$jA0$K!"%P%C%U%!$K$"$k$=$N%U%l!<%`(B
> $B$r=hM}$7$h$&$H$7$^$9!#(B
                $B$9$k$+$b$7$l$^$;$s!#(B
$B86J8$O!"(B
     When an interrupt is posted to signal that a
     frame has been received, it is possible that another frame might be in
     the process of being copied into the receive buffer while the driver is
     busy handling the first one. If the driver manages to finish processing
     the first frame before the chip is done DMAing the rest of the next
     frame, the driver may attempt to process the next frame in the buffer be-
     fore the chip has had a chance to finish DMAing all of it.
--
$BKY@nOBM:(B
