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To: FreeBSD-users-jp@jp.freebsd.org, kiyoshi_@pb.highway.ne.jp
From: Motomichi Matsuzaki <mzaki@e-mail.ne.jp>
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Subject: [FreeBSD-users-jp 44881] Re: unknown option? "IBM486"
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$B>>:j$G$9!#(B

From: "Kiyoshi Sato" <kiyoshi_@pb.highway.ne.jp>
Subject: [FreeBSD-users-jp 44880] unknown option? "IBM486"
Date: Fri, 13 Aug 1999 11:24:59 +0900

kiyoshi_> $BK\BN$OHs>o$K8E$$(BNEC$B$N(BPC-9801DS$B$G!"$b$H$b$H$O(B386SX$B$G$"$k$b$N$K!"(BIBM$B$N(B
kiyoshi_> BlueLightning(IBM486SX)$B$r;HMQ$7$?(BOverDrive$B$r$+$V$;$F;HMQ$7$F$$$^$9!#(B
kiyoshi_> $B0J2<$K;HMQ$7$F$$$k(BPC$B$N9=@.$r<($7$^$9!#(B

$B%O%s%I%V%C%/$N5-:\$,8E$$2DG=@-$,$"$j$^$9!#(B
$B$?$7$+(B non-Intel CPU $B$N%5%]!<%H$O(B FreeBSD(98) $B$+$iK\2H$X%^!<%8$5$l$F!"(B
$B:Y$+$$$H$3$m$,$$$m$$$m$H=q$-JQ$o$C$F$$$k$N$G$O$J$$$+$H;W$$$^$9!#(B

/usr/src/sys/i386/conf/LINT $B$h$j!"(B

#
# Options for CPU features.
#
# CPU_BLUELIGHTNING_FPU_OP_CACHE enables FPU operand cache on IBM
# BlueLightning CPU.  It works only with Cyrix FPU, and this option
# should not be used with Intel FPU.
#
# CPU_BLUELIGHTNING_3X enables triple-clock mode on IBM Blue Lightning 
# CPU if CPU supports it. The default is double-clock mode on
# BlueLightning CPU box.  
#
# CPU_BTB_EN enables branch target buffer on Cyrix 5x86 (NOTE 1).
#
# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
# mapped mode.  Default is 2-way set associative mode.
#
# CPU_CYRIX_NO_LOCK enables weak locking for the entire address space
# of Cyrix 6x86 and 6x86MX CPUs.  If this option is not set and
# FAILESAFE is defined, NO_LOCK bit of CCR1 is cleared.  (NOTE 3)
#
# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
# reorder).  This option should not be used if you use memory mapped
# I/O device(s). 
#
# CPU_FASTER_5X86_FPU enables faster FPU exception handler.
#
# CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products
# for i386 machines. 
#
# CPU_IORT defines I/O clock delay time (NOTE 1).  Default vaules of
# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
# (no clock delay).
#
# CPU_LOOP_EN prevents flushing the prefetch buffer if the destination
# of a jump is already present in the prefetch buffer on Cyrix 5x86(NOTE
# 1). 
#
# CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1).
#
# CPU_SUSP_HLT enables suspend on HALT.  If this option is set, CPU
# enters suspend mode following execution of HALT instruction.
#
# CPU_WT_ALLOC enables write allocation on Cyrix 6x86/6x86MX and AMD
# K5/K6/K6-2 cpus.
#
# CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache
# flush at hold state.
#
# CYRIX_CACHE_REALLY_WORKS enables (1) CPU cache on Cyrix 486 CPUs
# without cache flush at hold state, and (2) write-back CPU cache on
# Cyrix 6x86 whose revision < 2.7 (NOTE 2).
#
# NO_F00F_HACK disables the hack that prevents Pentiums (and ONLY
# Pentiums) from locking up when a LOCK CMPXCHG8B instruction is
# executed.  This should be included for ALL kernels that won't run
# on a Pentium.
#
# NO_MEMORY_HOLE is an optimisation for systems with AMD K6 processors
# which indicates that the 15-16MB range is *definitely* not being 
# occupied by an ISA memory hole.
#
# NOTE 1: The options, CPU_BTB_EN, CPU_LOOP_EN, CPU_IORT,
# CPU_LOOP_ENand CPU_RSTK_EN should not be used becasue of CPU bugs.
# These options may crash your system. 
#
# NOTE 2: If CYRIX_CACHE_REALLY_WORKS is not set, CPU cache is enabled
# in write-through mode when revision < 2.7.  If revision of Cyrix
# 6x86 >= 2.7, CPU cache is always enabled in write-back mode.
#
# NOTE 3: This option may cause failures for software that requires
# locked cycles in order to operate correctly.
#

$B$H$N$3$H$G$9!#(B

FreeBSD(98) $B$G$bF1$8$K$J$C$F$$$k$N$G$O$J$$$G$7$g$&$+!#(B

CPU_BLUELIGHTNING_FPU_OP_CACHE
CPU_BLUELIGHTNING_3X
CPU_I486_ON_386

$B$"$?$j$,4X78$"$j$=$&$G$9!#(B

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