

FINS_CV

f[^	DM	0
[GA	CIO	1
goN 0 ` C	EM0	10
	EM1	11
	EM2	12
	EM3	13
	EM4	14
	EM5	15
	EM6	16
	EM7	17
	EM8	18
	EM9	19
	EMA	20
	EMB	21
	EMC	22
PLCXe[^XGA	PLCST	90
PLCvGA	PLCTM	91


FINS

f[^	DM	0
[GA	CIO	1
HR[GA	HR	2
WR[GA	WR	3
goN 0 ` C	EM0	10
	EM1	11
	EM2	12
	EM3	13
	EM4	14
	EM5	15
	EM6	16
	EM7	17
	EM8	18
	EM9	19
	EMA	20
	EMB	21
	EMC	22
PLCXe[^XGA	PLCST	90
PLCvGA	PLCTM	91


MC1E

D f[^WX^(word)	D	0
M [GA(bit)	M	1
X ̓[GA(bit)	X	2
Y o̓[GA(bit)	Y	3
B N[GA(bit)	B	4
ZR t@CWX^(word)	R	10
W NWX^(word)	W	11


MC3E

D f[^WX^(word)	D	0
M [GA(bit)	M	1
X ̓[GA(bit)	X	2
Y o̓[GA(bit)	Y	3
B N[GA(bit)	B	4
L b`[GA(bit)	L	5
ZR t@CWX^(word)	R	10
W NWX^(word)	W	11
ꃊ[GA(bit)	SM	90

