include $(NOODLYBOX_HOME)/etc/makerule

CPROGRAM=accessfpga
TOP_UNIT=tSAMPLEFPGA

FSMARGS=-l verilog -c ../c/$(CPROGRAM)

FUSEFLAGS=-lib unisims_ver

all : $(TOP_UNIT).prj

clean :
	-rm -rf isim isim.tmp_save
	-rm -f  *.log *.log_back *.xwv *$(DOTEXE) *.prj

makefile : ../isesimv_makefile
	cd .. && $(MAKE) isesimv/$@

$(TOP_UNIT).prj : ../create_isesimproj.tcl ../rtl/MAINDCM.v
	xtclsh $< verilog > $@

../c/$(CPROGRAM)$(DOTEXE) :
	cd ../c && $(MAKE)

$(CPROGRAM).xwv : $(TOP_UNIT)$(DOTEXE) ../c/$(CPROGRAM)$(DOTEXE)
	FSMARGS="$(FSMARGS)" ./$< -tclbatch $(NOODLYBOX_HOME)/tcl/fsm.tcl -wavefile $@

view : $(CPROGRAM).xwv
	isimwave $<
