
//	Start

	break;
	case _ROAST_SIMD_CORE__XMM_XMM__1NUM:
	{
		switch(from_xmm_num)
		{
			case -99:

			_ROAST_SIMD_CORE__XMM_M128_GEN1(_ROAST_SIMD_CORE__XMM_XMM__1NUM, 0)
			_ROAST_SIMD_CORE__XMM_M128_GEN1(_ROAST_SIMD_CORE__XMM_XMM__1NUM, 1)
			_ROAST_SIMD_CORE__XMM_M128_GEN1(_ROAST_SIMD_CORE__XMM_XMM__1NUM, 2)
			_ROAST_SIMD_CORE__XMM_M128_GEN1(_ROAST_SIMD_CORE__XMM_XMM__1NUM, 3)
			_ROAST_SIMD_CORE__XMM_M128_GEN1(_ROAST_SIMD_CORE__XMM_XMM__1NUM, 4)
			_ROAST_SIMD_CORE__XMM_M128_GEN1(_ROAST_SIMD_CORE__XMM_XMM__1NUM, 5)
			_ROAST_SIMD_CORE__XMM_M128_GEN1(_ROAST_SIMD_CORE__XMM_XMM__1NUM, 6)
			_ROAST_SIMD_CORE__XMM_M128_GEN1(_ROAST_SIMD_CORE__XMM_XMM__1NUM, 7)
	#ifdef _M_AMD64
			_ROAST_SIMD_CORE__XMM_M128_GEN1(_ROAST_SIMD_CORE__XMM_XMM__1NUM, 8)
			_ROAST_SIMD_CORE__XMM_M128_GEN1(_ROAST_SIMD_CORE__XMM_XMM__1NUM, 9)
			_ROAST_SIMD_CORE__XMM_M128_GEN1(_ROAST_SIMD_CORE__XMM_XMM__1NUM, 10)
			_ROAST_SIMD_CORE__XMM_M128_GEN1(_ROAST_SIMD_CORE__XMM_XMM__1NUM, 11)
			_ROAST_SIMD_CORE__XMM_M128_GEN1(_ROAST_SIMD_CORE__XMM_XMM__1NUM, 12)
			_ROAST_SIMD_CORE__XMM_M128_GEN1(_ROAST_SIMD_CORE__XMM_XMM__1NUM, 13)
			_ROAST_SIMD_CORE__XMM_M128_GEN1(_ROAST_SIMD_CORE__XMM_XMM__1NUM, 14)
			_ROAST_SIMD_CORE__XMM_M128_GEN1(_ROAST_SIMD_CORE__XMM_XMM__1NUM, 15)
#endif
		}
	}


#undef _ROAST_SIMD_CORE__XMM_XMM__1NUM

//	End
